eXplorersPal: xpal_board.h File Reference

Basic Board Definitions. More...

#include <avr/io.h>

Defines
#define	HL_SD_SS PB0
	SD card SPI Select Port bit.
#define	HL_SD_SS_PORT PORTB
	SD card SPI Select Port.
#define	HL_SD_SS_DDR DDRB
	SD card SPI Select Data Direction.
#define	HL_SD_SCK PB1
	SD card SPI Clock Port bit.
#define	HL_SD_SCK_PORT PORTB
	SD card SPI Clock Port.
#define	HL_SD_SCK_DDR DDRB
	SD card SPI Clock Data Direction.
#define	HL_SD_MOSI PB2
	SD card SPI MOSI Port bit.
#define	HL_SD_MOSI_PORT PORTB
	SD card SPI MOSI Port.
#define	HL_SD_MOSI_DDR DDRB
	SD card SPI MOSI Data Direction.
#define	HL_SD_MISO PB3
	SD card SPI MISO Port bit.
#define	HL_SD_MISO_PIN PINB
	SD card SPI MISO Port.
#define	HL_SD_MISO_DDR DDRB
	SD card SPI MISO Data Direction.
#define	HL_EX232_UDR UDR3
	External RJ11 serial port Data Register.
#define	HL_EX232_UCSRA UCSR3A
	External RJ11 serial port Control Status A.
#define	HL_EX232_UCSRB UCSR3B
	External RJ11 serial port Control Status B.
#define	HL_EX232_UCSRC UCSR3C
	External RJ11 serial port Control Status C.
#define	HL_EX232_UBR UBR3
	External RJ11 serial port Baud Rate Reg.
#define	HL_EX232_CTL_PORT PORTL
	External RJ11 serial port Line Driver Control Port.
#define	HL_EX232_CTL_DDR DDRL
	External RJ11 serial port Line Driver Control Data Dir.
#define	HL_EX232_CTL_PIN PINL
	External RJ11 serial port Line Driver Control Input.
#define	HL_EX232_INVAL (PL5)
	External RJ11 serial port Line Driver Invalid Signal bit.
#define	HL_EX232_FRCON (PL6)
	External RJ11 serial port Line Driver ForceOn Signal bit.
#define	HL_EX232_EN (PL7)
	External RJ11 serial port Line Driver Enable bit.
#define	HL_MOD_UDR UDR2
	GPS Module USART Data Register.
#define	HL_MOD_UCSRA UCSR2A
	GPS Module USART Control Status A.
#define	HL_MOD_UCSRB UCSR2B
	GPS Module USART Control Status B.
#define	HL_MOD_UCSRC UCSR2C
	GPS Module USART Control Status C.
#define	HL_MOD_UBR UBR2
	GPS Module USART Baud Rate Reg.
#define	HL_PWR_VLCD 0
	LCD HV regulator enable bit.
#define	HL_PWR_VLCD_PORT PORTL
	LCD HV regulator enable Port.
#define	HL_PWR_VLCD_DDR DDRL
	LCD HV regulator enable data direction.
#define	HL_PWR_VCC5 1
	5V regulator enable bit
#define	HL_PWR_VCC5_PORT PORTL
	5V regulator enable Port
#define	HL_PWR_VCC5_DDR DDRL
	5V regulator enable data dir.
#define	HL_PWR_VCC33 2
	3.3V regulator enable bit
#define	HL_PWR_VCC33_PORT PORTL
	3.3V regulator enable port
#define	HL_PWR_VCC33_DDR DDRL
	3.3V regulator enable data dir.
#define	HL_PWR_ADMUX0 ( (_BV(REFS0)) \| (_BV(REFS1)) )
	ADC0, Vref=2.56V.
#define	HL_PWR_ADCSRB 0x00
#define	HL_KEY_COL0 0
	Key Matrix Column0 bit.
#define	HL_KEY_COL1 1
	Key Matrix Column1 bit.
#define	HL_KEY_COL2 2
	Key Matrix Column2 bit.
#define	HL_KEY_COL3 3
	Key Matrix Column3 bit.
#define	HL_KEY_COL_PORT PORTD
	Key Matrix Column Port.
#define	HL_KEY_COL_PIN PIND
	Key Matrix Column Input.
#define	HL_KEY_COL_DDR DDRD
	Key Matrix Column Data Dir.
#define	HL_KEY_COL_MASK 0x0F
	Key Matrix all Columns Bitmask.
#define	HL_KEY_ROW_A_ID 4
	Key Matrix Row Section A ID.
#define	HL_KEY_ROW_PORT_A PORTD
	Key Matrix Row Section A Port.
#define	HL_KEY_ROW_PIN_A PIND
	Key Matrix Row Section A Input.
#define	HL_KEY_ROW_DDR_A DDRD
	Key Matrix Row Section A Data Dir.
#define	HL_KEY_ROW0 4
	Key Matrix Row 0 bit.
#define	HL_KEY_ROW1 5
	Key Matrix Row 1 bit.
#define	HL_KEY_ROW2 6
	Key Matrix Row 2 bit.
#define	HL_KEY_ROW3 7
	Key Matrix Row 3 bit.
#define	HL_KEY_MASK_ROW_A 0xF0
	Key Matrix Row1..3 Bitmask.
#define	HL_KEY_ROW_B_ID 5
	Key Matrix Row Section B ID.
#define	HL_KEY_ROW_PORT_B PORTE
	Key Matrix Row Section B Port.
#define	HL_KEY_ROW_PIN_B PINE
	Key Matrix Row Section B Input.
#define	HL_KEY_ROW_DDR_B DDRE
	Key Matrix Row Section B Data Dir.
#define	HL_KEY_ROW4 0
	Key Matrix Row 4 bit.
#define	HL_KEY_ROW5 1
	Key Matrix Row 5 bit.
#define	HL_KEY_ROW6 2
	Key Matrix Row 6 bit.
#define	HL_KEY_ROW7 3
	Key Matrix Row 7 bit.
#define	HL_KEY_ROW8 4
	Key Matrix Row 8 bit.
#define	HL_KEY_ROW9 5
	Key Matrix Row 9 bit.
#define	HL_KEY_ROW10 6
	Key Matrix Row 10 bit.
#define	HL_KEY_ROW11 7
	Key Matrix Row 11 bit.
#define	HL_KEY_MASK_ROW_B 0xFF
	Key Matrix Row4..11 Bitmask.
#define	HL_KEY_ROW_C_ID 6
	Key Matrix Row Section C ID.
#define	HL_KEY_ROW_PORT_C PORTH
	Key Matrix Row Section C Port.
#define	HL_KEY_ROW_PIN_C PINH
	Key Matrix Row Section C Input.
#define	HL_KEY_ROW_DDR_C DDRH
	Key Matrix Row Section C Data Dir.
#define	HL_KEY_ROW12 2
	Key Matrix Row 12 bit.
#define	HL_KEY_ROW13 3
	Key Matrix Row 13 bit.
#define	HL_KEY_ROW14 4
	Key Matrix Row 14 bit.
#define	HL_KEY_ROW15 5
	Key Matrix Row 15 bit.
#define	HL_KEY_ROW16 6
	Key Matrix Row 16 bit.
#define	HL_KEY_ROW17 7
	Key Matrix Row 17 bit.
#define	HL_KEY_MASK_ROW_C 0xFC
	Key Matrix Row12..17 Bitmask.
#define	HL_USB_BASE_ADR 0x4000
	Address range start in External Memory.
#define	HL_USB_ADR_LENGTH 0x3FFF
	Address range length in External Memory.
#define	HL_USB_TXE 4
	bit to access FT245 TXE (Data can be writen to USB)
#define	HL_USB_TXE_PIN PINB
	Input to access FT245 TXE.
#define	HL_USB_TXE_DDR DDRB
	Data Dir. to access FT245 TXE.
#define	HL_USB_RXF 5
	bit to access FT245 RXF (Data available from USB)
#define	HL_USB_RXF_PIN PINB
	Input to access FT245 RXF.
#define	HL_USB_RXF_DDR DDRB
	Data Dir. to access FT245 RXF.
#define	HL_USB_PWREN 6
	bit to access FT245 PwrEnable (USB is connected)
#define	HL_USB_PWREN_PIN PINB
	Input to access FT245 PwrEnable.
#define	HL_USB_PWREN_DDR DDRB
	Data Dir. to access FT245 PwrEnable.
#define	HL_USB_RESET 7
	bit to control FT245 RESET
#define	HL_USB_RESET_PORT PORTB
	Port to control FT245 RESET.
#define	HL_USB_RESET_DDR DDRB
	Data Dir. to control FT245 RESET.
#define	HL_LCD_DATA_PORT PORTK
	LCD Data Port [out].
#define	HL_LCD_DATA_PIN PINK
	LCD Data Input.
#define	HL_LCD_DATA_DDR DDRK
	LCD Data Direction.
#define	HL_LCD_RESET 2
	bit to control LCD RESET
#define	HL_LCD_RESET_PORT PORTJ
	Port to control LCD RESET.
#define	HL_LCD_RESET_DDR DDRJ
	Data Dir. to control LCD RESET.
#define	HL_LCD_CS 3
	bit to control LCD Select
#define	HL_LCD_CS_PORT PORTJ
	Port to control LCD Select.
#define	HL_LCD_CS_PIN PINJ
	Input to control LCD Select (write = toggle).
#define	HL_LCD_CS_DDR DDRJ
	Data Dir. to control LCD Select.
#define	HL_LCD_D_R 4
	bit to control LCD Data/Register access
#define	HL_LCD_D_R_PORT PORTJ
	Port to control LCD Data/Register access.
#define	HL_LCD_D_R_DDR DDRJ
	Data Dir. to control LCD Data/Register access.
#define	HL_LCD_WR 5
	bit to control LCD Write
#define	HL_LCD_WR_PORT PORTJ
	Port to control LCD Write.
#define	HL_LCD_WR_PIN PINJ
	Input to control LCD Write (write = toggle).
#define	HL_LCD_WR_DDR DDRJ
	Data Dir. to control LCD Write.
#define	HL_LCD_RD 6
	bit to control LCD Read
#define	HL_LCD_RD_PORT PORTJ
	Port to control LCD Read.
#define	HL_LCD_RD_PIN PINJ
	Input to control LCD Read (write = toggle).
#define	HL_LCD_RD_DDR DDRJ
	Data Dir. to control LCD Read.
#define	HL_EXRAM_START 0x8000
	External RAM Start Address.
#define	HL_EXRAM_END 0xFFFF
	External RAM End Address.
#define	HL_ADRH_PORT PORTC
	External RAM Address Port.
#define	HL_ADRH_DDR DDRC
	External RAM Address Data Direction.
#define	HL_XMCRA (_BV(SRE)\|_BV(SRL2))
	RAM interface configuration with no wait states.
#define	HL_XMCRB _BV(XMBK)
	RAM interface to support full addr. range (incl. USB), bus keeper on.

Detailed Description

Basic Board Definitions.

This header file is providing definitions for IO pins and functional block connections. The definitions are written to use the c-lib _BV macro

xpal_board.h File Reference

Defines

Detailed Description