usarts_int.h File Reference

USART access - internal definitions. More...

#include "xpal_power.h"

Go to the source code of this file.

Defines
#define	UCSRnA(UC)   (UC->base[0])
	USART control/status register A.
#define	UCSRnB(UC)   (UC->base[&UCSR0B-&UCSR0A])
	USART control/status register B.
#define	UCSRnC(UC)   (UC->base[&UCSR0C-&UCSR0A])
	USART control/status register C.
#define	UBRRnL(UC)   (UC->base[&UBRR0L-&UCSR0A])
	USART baud rate register (low part).
#define	UBRRnH(UC)   (UC->base[&UBRR0H-&UCSR0A])
	USART baud rate register (high part).
#define	UBRRn(UC)   (*((volatile uint16_t *)(&UC->base[(volatile uint8_t*)&UBRR0-&UCSR0A])))
	USART baud rate register.
#define	UDRn(UC)   (UC->base[&UDR0-&UCSR0A])
	USART data register.
#define	USART_DEF_CTRL(N)
	USART control structure.
#define	USART_DEF_RXINT(N)
	USART RX interrupt handler.
#define	USART_DEF_TXINT(N)
	USART TX interrupt handler (data register empty).
#define	USART_DEF_TXCINT(N)
	USART TX interrupt handler (transmit complete).

---

Detailed Description

USART access - internal definitions.

---

Define Documentation

#define USART_DEF_CTRL

(

N

)

Value:

static const char usart_name_##N[] PROGMEM = "USART"#N;         \
  usart_control_t usart_control_##N =                                   \
    { .name = usart_name_##N,                                           \
      .base = (uint8_t * const)&(UCSR##N##A),                           \
      .prr = (N == 0 ? &PRR0 : &PRR1),                                  \
      .prusart = _BV(PRUSART##N),                                       \
    };

USART control structure.

#define USART_DEF_RXINT

(

N

)

Value:

extern usart_control_t usart_control_##N;                               \
  ISR(USART##N##_RX_vect,ISR_BLOCK)                                     \
  {                                                                     \
        /*debug thomas*/        \
        DDRH |= 0x40;           \
        PORTH |= 0x40;          \
    usart_control_t * const uc = &usart_control_##N;                    \
    uint8_t st = UCSR##N##A;                                            \
    /* make sure FIFO buffer is usable */                               \
    hl_wakeup_memory ();                                                \
    /* loop until hardware RX buffer is empty - reduces INT load */     \
    do {                                                                \
      fifo_item_t it;                                                   \
      it.flags = ((st & _BV(FE0)) ? USART_FRAME_ERROR : 0)              \
        | ((st & _BV(UPE0)) ? USART_PARITY_ERROR : 0);                  \
      it.data = UDR##N;                                                 \
      if (it.data == uc->ts_trigger) {                                  \
        uc->timestamp = TCNT2;                                          \
        it.flags |= USART_TIMESTAMPED;                                  \
      }                                                                 \
      fifo_putQ_item (&uc->rxbuf, it);                                  \
    } while(((st = UCSR##N##A) & _BV(RXC##N)));                         \
    hl_pwr_SetWakeSource (HL_PWR_WAKE_BY_USART##N);                     \
        /*debug thomas*/                \
        PORTH &= ~(0x40);               \
  }

USART RX interrupt handler.

#define USART_DEF_TXCINT

(

N

)

Value:

extern usart_control_t usart_control_##N;                               \
  ISR(USART##N##_TX_vect)                                               \
  {                                                                     \
    usart_control_t * const uc = &usart_control_##N;                    \
    uc->tx_empty = 1;                                                   \
    hl_pwr_SetWakeSource (HL_PWR_WAKE_BY_USART##N);                     \
  }

USART TX interrupt handler (transmit complete).

#define USART_DEF_TXINT

(

N

)

Value:

extern usart_control_t usart_control_##N;                               \
  ISR(USART##N##_UDRE_vect,ISR_BLOCK)                                   \
  {                                                                     \
    usart_control_t * const uc = &usart_control_##N;                    \
    /* make sure FIFO buffer is usable */                               \
    hl_wakeup_memory ();                                                \
    /* refill hardware buffer from FIFO */                              \
    if (!fifo_is_empty (&uc->txbuf)) {                                  \
      UDR##N = (uint8_t)fifo_getQ_item (&uc->txbuf).data;               \
      if (!fifo_is_empty (&uc->txbuf)) {                                \
        return;                                                         \
      }                                                                 \
    }                                                                   \
    /* disable further interrupts as we have no new data yet */         \
    UCSR##N##B &= ~_BV(UDRIE##N);                                       \
    hl_pwr_SetWakeSource (HL_PWR_WAKE_BY_USART##N);                     \
  }

USART TX interrupt handler (data register empty).